The present invention relates to clock receiver designs. Clock receivers can be used in high speed digital to analog converters, analog to digital converters, and clock distribution circuits which, in turn, are provided in integrated circuits. These high speed components typically operate in about the 1-5 GHz frequency range but can operate as low as 100 MHz. Performance of CMOS clock receivers can be severely impacted by duty cycle errors and cross point errors, which cause interference in the receiver such as phase noise, jitter, and frequency limit problems. Embodiments of the present invention address solutions to reduce duty cycle errors and cross point errors in CMOS clock receivers.
High speed clocked circuit systems often are driven by externally supplied clock systems. When circuit systems operate at clock speeds of 100 MHz-5 GHz or more, input clock signals usually are not provided as conventional square wave signals. Instead, the input clock signals often are differential signals that approximate sinusoids much closer than square waves. They often are “small swing” signals, having signal amplitudes that are smaller than the voltage sources (VDD) present within the circuit systems. Moreover, the input clock signals cannot be guaranteed to have a 50% duty cycle; instead, the two phases Φ1 and Φ2 of a clock signal have different durations. FIG. 1 illustrates an example of differential signals with different duty cycles. From such inputs, it becomes a challenge for circuit designers to generate clock signal that provide rail-to-rail swings (VDD to ground) with a proper 50% duty cycle.
Designers of high speed circuit systems face other challenges from the sinusoidal clock inputs. For example, some circuit systems require a full swing CMOS square wave with controlled cross points. A clock generator must convert a differential sinusoid signal to a rail-to-rail CMOS clock signal with controllable cross points, regardless of the cross points that are presented in the differential clock signal. FIG. 2 illustrates an example where cross points of differential input signals deviate from an ideal cross-point.
Accordingly, the inventors have identified a need in the art for a clock generator system that can manage duty cycles of a differential input clock and correct for asymmetry in such duty cycles. Moreover, the inventors have identified a need in the art for a clock generator that can detect and manage cross points of a differential input clock and correct such cross points when they deviate from ideal levels.